The present invention relates to a method for manufacturing semiconductor elements each configured in such a manner that an element isolation layer is formed in an SOI layer of an SOI (Silicon On Insulator) substrate by a LOCOS (Local Oxidation of Silicon) method.
An SOI type semiconductor device is formed on an SOI substrate in which a support substrate, an insulating layer (buried oxide film) and a silicon thin film layer (called “SOI layer”) made of monocrystalline silicon are sequentially formed. It is known that owing to an SOI structure, complete separation between elements becomes easy and a soft error and latch-up can be suppressed. Since the junction capacitance of a source/drain region can be reduced, such a technique has been used in the manufacture of many semiconductor devices as a technique that makes a contribution to speeding up and a reduction in power consumption.
Semiconductor elements have been micro-fabricated corresponding to densification of each of recent semiconductor devices. An SOI substrate in which the thickness of an SOI layer for forming each semiconductor element is set to 50 nm (nanometers) or less, has been mainstream.
On the other hand, a LOCOS method is known as one method for forming an element isolation layer on a normal silicon semiconductor substrate to insulate and isolate between semiconductor elements. This has been utilized as a method for forming an element isolation layer in an SOI layer relatively thick in thickness.
When the element isolation area is formed in the SOI layer relatively thick in thickness, a silicon nitride film is formed over the SOI layer through a pad oxide film interposed therebetween prior to the formation of the element isolation area. These are anisotropically etched to expose the SOI layer comprised of silicon. The exposed silicon is dry-oxidized by the LOCOS method to generate and form an insulating film comprised of silicon dioxide (SiO2).
On the other hand, there is known, as a method for performing etching on a thin-film SOI layer, an example wherein when sidewall spacers comprised of silicon dioxide are formed on their corresponding sidewalls of a gate electrode of a MOS element, a silicon dioxide film formed on the upper surface of the gate electrode is etched by 70 to 90% of its thickness and thereafter the remaining silicon dioxide is removed by plasma etching high in silicon selection ratio to thereby remove the silicon dioxide film on the upper surface of the gate electrode, whereby tail shaping due to the deposition of a superimposed film at the sidewalls of the gate electrode is prevented (refer to, for example, a patent document 1 (Japanese Patent Laid-Open No. 2002-237603 (paragraphs 0031-00036 in the fifth page, and FIG. 6)).
However, there is a risk that when the SOI layer is thinned up to 50 nm or less for the purpose of miniaturization of the semiconductor device, even the SOI layer is removed when the silicon nitride film (oxidation-resistant mask layer) laminated prior to the formation of the element isolation layer is anisotropically etched. When the SOI layer is removed without remaining, for instance, the formation of the insulating film by silicon dioxide using the LOCOS method becomes difficult, and the insulation/separation between semiconductor elements becomes incomplete, so that a short circuit occurs between the adjacent semiconductor elements, thus causing a problem that the reliability of the semiconductor device is degraded.